Firmware Guide (UK) (Disk 3 face 2) (19xx) [UTILITAIRE].dsk
HexaDumpAscii only
000000: 45 58 54 45 4E 44 45 44 20 43 50 43 20 44 53 4B EXTENDED CPC DSK
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007D40: 20 20 20 20 20 20 20 41 70 70 65 6E 64 69 78 20 Appendix
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007E10: 20 20 20 20 20 20 20 41 70 70 65 6E 64 69 78 20 Appendix
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007F80: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
007F90: 20 20 41 70 70 65 6E 64 69 78 20 36 2E 34 22 01 Appendix 6.4".
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007FF0: 16 2C EA 28 16 29 22 41 4D 53 54 52 41 44 20 43 .,.(.)"AMSTRAD C
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008020: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
008030: 20 41 70 70 65 6E 64 69 78 20 36 2E 35 22 01 9F Appendix 6.5"..
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008210: 41 4D 53 54 52 41 44 20 43 50 43 34 36 34 2F 36 AMSTRAD CPC464/6
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008230: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
008240: 20 20 20 20 20 20 20 20 20 20 41 70 70 65 6E 64 Append
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008700: 20 20 20 20 20 64 65 73 63 72 69 70 74 69 6F 6E description
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021420: 20 20 20 20 20 20 53 74 61 72 74 20 41 64 64 72 Start Addr
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021530: 1C 00 C4 02 00 00 00 02 1C 00 C5 02 00 00 00 02 ................
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021610: 20 20 20 58 20 20 20 20 20 20 20 20 58 20 20 20 X X
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0217F0: 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
021800: 20 20 41 70 70 65 6E 64 69 78 20 31 32 2E 33 0D Appendix 12.3.
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02AF00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF10: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF20: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF30: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF40: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF60: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF70: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF80: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AF90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AFA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AFB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AFC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AFD0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AFE0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02AFF0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B000: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B010: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B020: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B030: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B040: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B050: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B060: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B070: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B080: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B090: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B0A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B0B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B0C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B0D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B0E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B0F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B100: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B110: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B120: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B130: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B140: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B150: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B160: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B170: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B180: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B190: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B1A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B1B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B1C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B1D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B1E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B1F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B200: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B210: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B220: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B230: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B240: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B250: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B260: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B270: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B280: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B290: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B2A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B2B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B2C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B2D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B2E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B2F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B300: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B310: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B320: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B330: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B340: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B350: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B360: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B370: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B380: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B390: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B3A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B3B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B3C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B3D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B3E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B3F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B400: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B410: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B420: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B430: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B440: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B450: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B460: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B470: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B480: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B490: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B4A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B4B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B4C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B4D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B4E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B4F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B500: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B510: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B520: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B530: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B540: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B550: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B560: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B570: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B580: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B590: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B5A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02B5C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B5D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B5E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B5F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B600: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B610: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B620: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B630: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B640: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B650: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B660: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B670: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B680: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B690: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B6A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B6B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B6C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B6D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B6E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B6F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B700: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B710: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B720: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B730: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B740: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B750: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B760: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B770: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B780: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B790: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B7A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02B7C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02B7E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B7F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B800: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B810: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02B880: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02B890: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02B8F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02BA00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02D4F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D500: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D510: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D520: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D530: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D540: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D550: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D560: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D570: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D580: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D590: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D5A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D5B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D5C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D5D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D5E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D5F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D600: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D610: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D620: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D630: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D640: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D650: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D660: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D670: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D680: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D690: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D6A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D6B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D6C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D6D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D6E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D6F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D700: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D710: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D720: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D730: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D740: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D750: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D760: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D770: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D780: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D790: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D7A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D7B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D7C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D7D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D7E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D7F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D800: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D810: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D820: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D830: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D840: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D850: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D860: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D870: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D880: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D890: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D8A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D8B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D8C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D8D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D8E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D8F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D900: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D910: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D920: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D930: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D940: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D950: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D960: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D970: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D980: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D990: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D9A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D9B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D9C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D9D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D9E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02D9F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA10: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA20: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA30: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA40: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA60: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA70: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA80: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DA90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DAA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DAB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DAC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DAD0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DAE0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DAF0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB10: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB20: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB30: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB40: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB60: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB70: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB80: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DB90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DBA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DBB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DBC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DBD0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DBE0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DBF0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC10: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC20: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC30: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC40: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC60: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC70: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC80: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DC90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DCA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DCB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DCC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DCD0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DCE0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DCF0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DD00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DD10: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DD20: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DD30: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DD40: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DD50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DD60: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02DD80: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DD90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DDA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DDB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DDC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DDD0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DDE0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DDF0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DE00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DE10: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DE20: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DE30: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DE40: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DE50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02DE80: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DE90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DEA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DEB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DEC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DED0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DEE0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DEF0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02DFA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DFB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02DFC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E000: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E010: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E080: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E090: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E0A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E0B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E0C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E0D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E0E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E0F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E100: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E160: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E170: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E180: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E190: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E1A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E1B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E1C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E1D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E1E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E1F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E200: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E220: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E230: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E240: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E250: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E260: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E270: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E280: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E290: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E2A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E2C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E300: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E320: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E330: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E350: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E370: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E380: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E390: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E3A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E3D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E400: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E4A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E4B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E4C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E4D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E4E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E4F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E500: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E510: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E520: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E530: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E540: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E560: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E570: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E580: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E590: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E5A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E5C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E5D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E5E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E5F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E600: 54 72 61 63 6B 2D 49 6E 66 6F 0D 0A 00 01 00 00 Track-Info......
02E610: 27 00 00 00 02 09 50 E5 27 00 C1 02 00 00 00 02 '.....P.'.......
02E620: 27 00 C2 02 00 00 00 02 27 00 C3 02 00 00 00 02 '.......'.......
02E630: 27 00 C4 02 00 00 00 02 27 00 C5 02 00 00 00 02 '.......'.......
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02E690: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
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02E720: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E740: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E750: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E770: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E780: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E790: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E7A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E7E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E800: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E870: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E880: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E890: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E8A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E8B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E900: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E970: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E980: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02E990: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02E9D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02EA00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02EA50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EA60: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EA70: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02EA90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02EB30: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
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02EE40: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EE50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EE60: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EE70: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EE80: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EE90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EEA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EEB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EEC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EED0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EEE0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EEF0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF00: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF10: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF20: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF30: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF40: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF50: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF60: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF70: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF80: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EF90: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EFA0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EFB0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EFC0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EFD0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EFE0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02EFF0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F000: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F010: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F020: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F030: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F040: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F050: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F060: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F070: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F080: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F090: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F0A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F0B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F0C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F0D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F0E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F0F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F100: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F110: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F120: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F130: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F140: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F150: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F160: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F170: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F180: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F190: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F1A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F1B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F1C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F1D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F1E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F1F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F200: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F210: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F220: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F230: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F240: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F250: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F260: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F270: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F280: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F290: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F2A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F2B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F2C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F2D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F2E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F2F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F300: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F310: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F320: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F330: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F340: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F350: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F360: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F370: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F380: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F390: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F3A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F3B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F3C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F3D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F3E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F3F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F400: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F410: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F420: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F430: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F440: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F450: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F460: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F470: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F480: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F490: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F4A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F4B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F4C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F4D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F4E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F4F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F500: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F510: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F520: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F530: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F540: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F550: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F560: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F570: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F580: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F590: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F5A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F5B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F5C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F5D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F5E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F5F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F600: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F610: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F620: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F630: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F640: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F650: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F660: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F670: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F680: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F690: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F6A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F6B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F6C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F6D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F6E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F6F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F700: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F710: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F720: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F730: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F740: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F750: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F760: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F770: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F780: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F790: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F7A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F7B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F7C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F7D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F7E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F7F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F800: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F810: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F820: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F830: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F840: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F850: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F860: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F870: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F880: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F890: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F8A0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F8B0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F8C0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F8D0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F8E0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
02F8F0: E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 E5 ................
RESULT OF SEARCH :
PRO=56 CHEA=0 COD=17 MUSI=0 COP=1 GRA=20 WRIT=30 198=0 199=0 STARTER=0 KBI=0 CAAV=0 L.TOURNIER=0
PRO=56 CHEA=0 COD=17 MUSI=0 COP=1 GRA=20 WRIT=30 198=0 199=0 STARTER=0 KBI=0 CAAV=0 L.TOURNIER=0
EXTENDED CPC DSK File SAMdisk120417( P12-13BOTINnop12-14BOTIN#qrstu6-5CHARSI
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APEN-12A6 APEN-8 FABAPEN-9 4GHIJKLMAPEN-9C NOAPEN12 ASAPEN6 ASAPEN6-A
APEN6-B APEN6-C !APEN8 ASCAPEN8-A INDEFAPEN9 ASPAPEN9-A INQRSAPEN9-B
INTUBLOCKS IN%"#$%&F-SYS INFRENCH IN0LINES IN'()*SET6-1 IN"+,-./SET6-2
IN%01234SETB6-2 IN#567896-5CHARSBINPRS$$$Z*K8!N#F#2 !KG (# #F#AOpyl0ppxpxpx0pxA
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0tp0yy0pxxpy0yxq0xxxaqxpxxy30Lpqp0p0 apqp800apq90p0C0cqqpq00cqqapq-07pcq600p70p6
0paZ080000000xx0088A000t000x00000000xxT1100a0a11800aa90xaaa08yC0a01a100a030a1-03
Y10a0600Y1070xxY130608Y110Wxyxyx0l00p000000A0004000p0000x000x001001La18000aXa900
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l330 P10001a18000aXa900a00C00a0a1000a0c30a1-0000a06000000700030600f010Wxxxyxxyx
x8xxxx8xyx8xxxxAx8xx x 8xxx4xxyxxxxxxx8xxx00pxxxxx8xyx9yx8yxxx0pxxx00p8090x0xpC0
xp0p00xpp-0x600pq70x60xxqW0ll0xxxx09yyx8y00x0x08p0x00000xx0xp0xx0xx8A0x8088x00x0
0pC0xx0xx0A0x0p0p00a0xx0x0xx0xp0000010x0x0x1C0810p001p-0x70080xxE0xx pRS$$$6-5CH
ARS$$$6-6CHA-BBINcf3633Z*K8!N#F#2 !KG (# #F#AR11166a1311100#a131110070"a1311100
070a13111000 a1311100370a13111007030a13111000703a131110030a131110030a131110071a0
13492/ $ / *0 + -0a00%a0$a0!a0"a0a0a0a00a0a088a$p0030c60$30c1#1c30 3c30!30c130
c330c3030c30 660c3061c300630c1$1a3c00p1q%001qc$301qc!301q"301qc0001qc301qc3001q6
vp01q6p01q7776p001a77!30c3c33730f0c33030300303003%f0c3303030030300 P3$f00c33030
3003031703!f0c330303003031703"f0c33033300303003c63f0c33033300303030c6317f0c33033
3003031703c63f0c33033300303030c6317f 0c33033300303003c63170f0c3303330030f00g36!3
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00)g01000a006-8CHAR $$$11g00001.g0c00001,g0001,g1700001+g000010gc000001.g170 P6
-9CHAR BINaav04lxvfvvlfvl3lZ*K8!N#F#2 !KG (# #F#AaEh O0Phl0080$lAl805l0fl080fb8
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ff4fflbfffff3ffflff6f06flvfffl#llv04lxvfvvlfvl3lvfvxvlAPEN6 BASpmm, "Please in
sert disc 1 side 1 and press any key.." P , ,fil"apen6-a" 2 "set6-1.bin", DUM
, s( ####,()"AMSTRAD CPC464/664/6128 FIRMWARE Appendix
6.1" &2"set6-2.bin", DUM,9 "setb6-2.bin", DUM, qF ##,()"AMSTRAD CPC464/664/6
128 FIRMWARE Appendix 6.2" "Pfil"apen6-b" Z"blocks.bin
", DUM, cd###,()"AMSTRAD CPC464/664/6128 FIRMWARE Ap
pendix 6.3" "nfil"apen6-c" +x"lines.bin", DUM, k ##,()"AMSTRAD CPC464/664/6128
FIRMWARE Appendix 6.4" ."6-5chars.bin", DUM, q li '#
#,()"AMSTRAD CPC464/664/6128 FIRMWARE Appendix 6.5" "6-
6cha-t.bin", DUM, li #."6-6cha-b.bin", DUM, q li ##,()"AMSTRAD CPC464/664/
6128 FIRMWARE Appendix 6.6" -"6-7char.bin", DUM, q li
%##,()"AMSTRAD CPC464/664/6128 FIRMWARE Appendix 6.7"
-"6-8char.bin", DUM, q li B##,()"AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 6.8" 2 "6-9char.bin", DUM, k li 2##,()"AMSTRAD CPC464/66
4/6128 FIRMWARE Appendix 6.9" "#"!"fil £#,#, li #"
#,,P,, £8M, , "Please insert disc 1 side 1 and press any key.." 6"start.bas"
li # Appendix VI Displayed Character Set. There
are 256 symbols in the displayed character set. All of these can be pri
nted, although it requires special effort to print characters 0. .31 whi
ch are often interpreted as control codes. The user can set the matrix f
or any or all characters (see section 4.6). The following lists des
cribe the default character set. The character set is split into a
number of areas for eases of P description 0..31
(#00..#1F) ASCII control codes. 32..127 (#20..#7F)
ASCII characters. 128..143 (#80..#8F) Block grap
hics. 144..159 (#90..#9F) Line graphics. 160
..191 (#A0..#BF) Further characters. 192..255 (#C0..#
FF) Miscellaneous graphic symbols. a. ASCII Control Codes.
There are 256 symbols in the displayed character set. All of the
c. Block Graphics. Characters 128..143 (#80..#8F) are a set of
block graphics. Each character is divided into four cells. Bits 0
..3 of the character number determine which cells are filled. If the
appropriate bit is set then the cell is filled in, otherwise it is left
blank. The cells are
Bit 0 Bit 1
Bit 2 Bit 3
block graphics. Each character iriate bit is set
then the cell is filled in, otherwise it is left blank. The cells are
Bit 0 Bit 1 d. Line Graphics
. Characters 144..159 (#90..#9F) are a set of line graphics. The lin
es join the centre of the character to the centre of an edge. Each of th
e lines is associated with a bit of the character number. If the bit is
set then the line is present, if the bit is not set then the line is
not present. The central block of the character is always set.
The lines are associated with bits as follows
BIT
0
BIT 3 BIT 1
BIT 2
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w p8w8-2 $$$ w8www8ww8ww w8www8wwwwpp Iw868w w6 Appendix VIII
Notes and Tone Periods. The tables which follow give the recomm
ended tone period settings for notes in the even tempered scale for the
full eight octave range. The period is calculated from the note freque
ncy as follows (since the period is given in 8 microsecond units)
Period 125000 / Frequency The frequ
ency for each note is calculated from International A as follows
P Frequency 440 * (2 (Octave + (N - 10) / 12 )
) where Octave is the octave number. 0 is t
he octave including International A (and middle C), -1
is the octave below, +1 is the octave above etc.
N is the note number. 1 is C, 2 is C#, 3 is D etc. T
he period is an integer value and so the frequency of the note pr
oduced is not exactly the required frequency. The relative error is giv
en in the tables below. This is calculated as follows Error (Requi
red frequency - Actual frequency) / Required frequency Note F
requency Period Error Octave -3 C
32.703 3822 #0EEE -0.007% C# 34.648
3608 #0E18 +0.007% D 36.708 3405 #0D4D
-0.007% D# 38.891 3214 #0C8E -0.004%
E 41.203 3034 #0BDA +0.009% F 43.654
2863 #0B2F -0.016% F# 46.249 2703 #0A8F
+0.009% G 48.999 2551 #09F7 -0.002%
G# 51.913 2408 #0968 +0.005% A 55.00
0 2273 #08E1 +0.012% A# 58.270 2145 #
0861 -0.008% B 61.735 2025 #07E9 +0.011%
AMSTRAD CPC464/664/6128 FIRMWARE Appendix 8
.1 Note Frequency Period Error O
ctave -2 C 65.406 1911 #0777 -0.0
07% C# 69.296 1804 #070C +0.007% D
73.416 1703 #06A7 +0.022% D# 77.782
1607 #0647 -0.004% E 82.407 1517 #05ED
+0.009% F 87.307 1432 #0598 +0.019%
F# 92.499 1351 #0547 -0.028% G 97.999
1276 #04FC +0.037% G# 103.826 1204 #04D4
+0.005% A 110.000 1136 #0470 -0.032%
A# 116.541 1073 #0431 +0.039% B 123.
471 1012 #03F4 -0.038% Note F
requency Period Error Octave -1 C
130.813 956 #03DC +0.046% C# 138.591
902 #0386 +0.007% D 146.832 851 #0353
-0.037% D# 155.564 804 #0324 +0.058%
E 164.814 758 #02F6 -0.057% F 174.614
716 #02CC +0.019% F# 184.997 676 #02A4
+0.046% G 195.998 638 #027E +0.037%
G# 207.652 602 #025A +0.005% A 220.0
00 568 #0238 -0.032% A# 233.082 536 #
0218 -0.055% B 246.942 506 #01FA -0.038%
AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 8.2 Note Frequency P
eriod Error Octave 0 C 261.626
478 #01DE +0.046% Middle C C# 277.183 451
#01C3 +0.007% D 293.665 426 #01AA +0.08
1% D# 311.127 402 #0192 +0.058% E
329.628 379 #017B -0.057% F 349.228
358 #0166 +0.019% F# 369.994 338 #0152 +
0.046% G 391.995 319 #013F +0.037% G
# 415.305 301 #012D +0.005% A 440.000
284 #011C -0.032% International A A# 466.164
268 #010C -0.055% B 493.883 253 #00FD
-0.038% Note Frequency Period
Error Octave 1 P C 523.251 239
#00EF +0.046% C# 554.365 225 #00E1 -0.215%
D 587.330 213 #00D5 +0.081% D#
622.254 201 #00C9 +0.058% E 659.255 1
90 #00BE +0.206% F 698.457 179 #00B3 +0.
019% F# 739.989 169 #00A9 +0.046% G
783.991 159 #009F -0.277% G# 830.609
150 #0096 -0.328% A 880.000 142 #008E
-0.032% A# 932.328 134 #0086 -0.055%
B 987.767 127 #007F +0.356%
AMSTRAD CPC464/664/6128 FIRMWARE Appendi
x 8.3 Note Frequency Period Error
Octave 2 C 1046.502 119 #0077 -0.
374% C# 1108.731 113 #0071 +0.229% D
1174.659 106 #006A -0.390% D# 1244.508
100 #0064 -0.441% E 1318.510 95 #005F
+0.206% F 1396.913 89 #0059 -0.543%
F# 1479.978 84 #0054 -0.548% G 1567.982
80 #0050 +0.350% G# 1661.219 75 #004B
-0.328% A 1760.000 71 #0047 -0.032%
A# 1864.655 67 #0043 -0.055% B 1975.
533 63 #003F -0.435% Note Fr
equency Period Error Octave 3 C
2093.004 60 #003C +0.462% C# 2217.461
56 #0038 -0.662% D 2349.318 53 #0035 -
0.390% D# 2489.016 50 #0032 -0.441% E
2637.021 47 #002F -0.855% F 2793.826
45 #002D +0.574% F# 2959.955 42 #002A
-0.548% G 3135.963 40 #0028 +0.350%
G# 3322.438 38 #0026 +0.992% A 3520.00
0 36 #0024 +1.357% A# 3729.310 34 #00
22 +1.417% B 3951.066 32 #0020 +1.134%
AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 8.4 Note Frequency P
eriod Error Octave 4 C 4186.009
30 #001E +0.462% C# 4434.922 28 #001C
-0.662% D 4698.636 27 #001B +0.469%
D# 4978.032 25 #0019 +0.441% E 5274.04
1 24 #0018 +0.246% F 5587.652 22 #00
16 -0.685% F# 5919.911 21 #0015 -0.548%
G 6271.927 20 #0014 +0.350% G# 664
4.875 19 #0013 +0.992% A 7040.000 18
#0012 +1.357% A# 7458.621 17 #0011 +1.417%
B 7902.133 16 #0010 +1.134% The notes
in the scale of C major are given in a slightly more digestible
form below. . ettin #0016 -0.685% F# 5919.911
21 #0015 -0.548% G 6271.927 20 #0014 +
0.350% G# 6644.875 19 #0013 +0.992% A
7040.000 18 #0012 APEN8 BASp #,,P,, £8Md , "Please insert
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IRMWARE Appendix 8.5" Z#F"!"fil £#,P#,Z P #,,P,, £8
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IX The Programmable Sound Generator. The programm
able sound generator (PSG) is an AY-3-8912 chip. This is briefly descr
ibed in section 7.1. The PSG has a number of registers which are desc
ribed below. This information is provided for the interest of the
user, particularly if hardware enveloping is to be used (in which c
ase section (e) will be of special interest). However, the software enve
loping provided by the Sound Manager can achieve all that the sound chi
p is capable unless very short attacks or decays are required.
If the user is intending to drive the sound chip directly rather than
by using the Sound Manager then the information presented is not
complete and the user should consult the manufacturer's data sheet.
The user is advised to call the routine MC SOUND REGISTER to write
data to a sound chip register as this ob Peys the timing constraints on
access to the sound chip. The following diagram indicates the i
nteractions between the various sections of the sound chip
Envelope Tone Enables
I/O Generator Generators -- (R7) ----- Port
(R11..R13) (R0..R5) (R14)
V
Amplitude
Digital to Noise Controls --- Analog -- Generator
(R8..R10) Converters (R6)
V
Outputs
AMSTRAD CPC464/664/6128 FIRMWARE Appendix 9.1
The sound chip data registers are as follows
Register 0 Channel A tone period fine tune. Register 1
Channel A tone period coarse tune. Register 2 Chann
el B tone period fine tune. Register 3 Channel B tone peri
od coarse tune. Register 4 Channel C tone period fine tune
. Register 5 Channel C tone period coarse tune.
Register 6 Noise period. Register 7 Enables an
d I/O direction. Register 8 Channel A amplitude and envelo
pe enable. Register 9 Channel B amplitude and envelope ena
ble. Register 10 Channel C amplitude and envelope enable.
Register 11 Envelope period fine tune. Register
12 Envelope period coarse tune. Register 13 Envelo
pe shape. Register 14 Input from or output to port A.
Register 15 Not used. a. Tone Generators (Registers
0..5) Each channel has two tone period registers associated with it.
These set the period of the sound to be generated (in units
of 8 microseconds) by that channel. The fine tune register stores the l
east significant 8 bits of the period the coarse tune register stores t
he most significant 4 bits of the period. To include the tone in th
e output of a channel the appropriate bit in the enables register must
be cleared. b. Noise Generator (Register 6). Ther
e is a single pseudo-random noise source. The output from this can be in
cluded in the output of any of the three channels (as specified by the
enables register). The period of the noise generator is set by bits 0.
.4 of the noise period register. The period specifies the middle f
requency of the noise produced in 8 microsecond units. c. Enables (R
egister 7). The enables register specifies whether tone or noise is to
be included in the output from each channel. It also specifies whethe
r the I/O port is to act in input or in output mode. The bits are all
ocated as follows Bit 0 Channel A tone disab
le. Bit 1 Channel B tone disable. B
it 2 Channel C tone disable. Bit 3 Channel A noise
disable. Bit 4 Channel B noise disable.
Bit 5 Channel C noise disable. Bit 6 Port A
output mode. Bit 7 Not used. AMSTRAD CPC4
64/664/6128 FIRMWARE Appendix 9.2 N
ote that port A is connected to the keyboard and joystick and so the po
rt must always be in input mode. The user must ensure that bit 6 of the
enables register is always set to zero. d. Amplitude Controls (Regist
ers 8..10). Each channel has an amplitude Pcontrol register associat
ed with it. Bit 4 of this register specifies whether hardware enveloping
is to be used for the channel. If the bit is set then the channel ampli
tude (volume) is under the control of the hardware envelope generator. I
f the bit is clear then the amplitude is set by bits 0..3 of the registe
r - a value of 0 means no sound and a value of 15 means maximum volume.
e. Envelope generator (Registers 11..13). The sound chip has
a single hardware envelope generator which can be used to control an
y combination of the three sound channels as specified by the cha
nnel's amplitude register (see (d) above). Bits 0 to 3 of register 13
control the shape of the envelope in a rather unobvious manner.
The following tables give values required to generate each of the
8 hardware envelopes that are possible. Other values (0..7) duplicat
e envelopes 9 and 15. (PSG) is an AYd." F P"pad2-5", "Z"joy2-5", d"Control
Translation Table.""The following diagram describes the translation when the co
ntrol key is pressed." n"2-6main", x"pad2-6", "joy2-6", 7#,,O,,#,,P,,#,,P,,
£8 Jfil"AP1-1" * "append-1.bas""464-AP1", "6128-ap1", T
he length of each of the ramps, upwards or downwards, is set by the en
velope period. The envelope period is a full 16 bit value whose less sig
nificant byte is stored in register 11 and whose most significant byte
is stored in register 12. The period is given in 128 microsecond units
and is the time between steps in the ramp. Since the ramp has 16 steps
(corresponding to the 16 volume settings) the total time taken for the
ramp is the envelope period times 1024 microseconds (i.e. the envelope
period approximately sets the total time for the ramp in milliseco
nds). f. I/O Port (Register 14). The mode of operation of th
e PSG port is set by a bit in the enables register (see section (c) ab
ove). However, since port A is dedicated to reading the keyboard and j
oysticks it should always be operated in input mode. The port may be re
ad by reading the contents of register 14. However, scanning the keybo
ard is a complex action and is best left to the Key Manager which pr
ovides ample facilities for access to the keys. References to
port B in the manufacturer's data sheet should be ignored as the
AY-3-8912 is a version of the chip that does not have port B.
AMSTRAD CPC464/664/6128 FIRMWARE Appendix 9.4
or downwards, is set by the envelope period. The envelope period is .
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3333f633333333e Appendix X Kernel Block Layouts.
The user provides a number of blocks to the Kernel for various
purposes. The layouts of these blocks are described below, mainly for t
he interest of the user. There are very few occasions when the user is
allowed to write to one of these blocks. Routines are provided to per
form most actions that the user could wish to perform (see KL INIT EVEN
T, KL ADD TICKER, KL NEW FRAME FLY, KL NEW FAST TICKER and KL DISAR
M EVENT). These routines set values into the block from regist
ers. The user should not write to the blocks, except as noted below.
All the following blocks must lie in the central 32K of RAM (otherwise
the Kernel will be unable to access them). On the CPC6128 the
user is advised to keep these blocks in RAM block 2 if any bank switchi
ng is being performed (see section 2.5). a. Event Blocks. Se
e section 12 for a general discussion of events and event blocks. An
event block is laid out as follows
0,1 Chain
2
Count
3 Class
4,5 Routine address
6
ROM
7+ User fields
Chain is a system pointer which
must never be written to by the user. It is used to store events on the
various event queue. Class records the type of the event. It should n
ot be written to by the user. Bit 0 1 Near
address, 0 Far address. Bits 1..4 Synchronous event priori
ty. Bit 5 Must be zero. Bit 6 1
Express event, 0 Normal event. Bit 7 1 Asynchronous e
vent, 0 Synchronous event. AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 10.1 Note that many system queues ar
e kept in priority order and so the block must be requed if the prio
rity is changed, it is not sufficient merely to change the priority in
the event block. Count is the event count - a record of how many kicks
are waiting to be processed or whether the event is disabled. See sec
tion 12.2 for a full discussion of the use of the event count.
Routine address and ROM make up the far address of the event routine.
If the near address bit in the event class is true then the event is
at a near address - the ROM select byte (byte 6) is ignored and the e
vent routine is called directly. If the near address bit is false th
en the event routine is at a far address - bytes 4, 5 and 6 make up the
far address to call to run the event routine. The user may write to t
he routine address and ROM fields (and to the near address bit in the c
lass byte as well) provided that the operation is performed indivi
sibly (i.e. interrupts should be disabled). The user fields are option
al. They may be used to provide a data area specific to the event block
so that a single event routine may be shared between a number of d
ifferent event blocks ( Pthe event routine is passed the address of t
he user fields). b. Ticker Queue Blocks. See section 11 for
a general discussion of ticker interrupts and the ticker queue. A tick
er queue block is laid out as follows
0,1 Tick chain
2,3 Tick count
4,5 Recharge count
6
+ Event block
Tick chain is a system pointer which must never be written to by the
user. It is used to store the block on the ticker queue. Tick count is
a count of the number of ticks before the next kick occurs. A tick
count of zero means that the tick block is dormant and will not genera
te any kicks. (Ideally a dormant block should be removed from the
ticker queue to avoid wasting time). The user may write to this fie
ld is required providing this is done indivisibly. Recharge count is t
he value that the tick count is set to after each kick. If the recharg
e count is zero then the ticker block will become dormant after generat
ing one kick. The user may write to this field is required providing thi
s is done indivisibly. Event block is a standard event block as desc
ribed in section (a) above. AMSTRAD CPC464/664/6128 FIRMWAR
E Appendix 10.2 c. Frame Flyback Que
ue Blocks. See section 11 for a general discussion of frame flybac
k interrupts and the frame flyback queue. A frame flyback queue block i
s laid out as follows
0,1 Frame chain
2+
Event block F
rame chain is a system pointer which must never be written to by the us
er. It is used to store the block on the frame flyback queue. Event
block is a standard event block as described in section (a) above.
d. Fast Ticker Queue Blocks. See section 11 for a genera
l discussion of fast ticker interrupts and the fast ticker queue. A fas
t ticker queue block is laid out as follows
0,1 F
ast chain
2+ Event block
Fast chain is a system pointer which must never be written
to by the user. It is used to store the block on the fast ticker queue
. Event block is a standard event block as described in section
(a) above. AMSTRAD CPC464/664/6128 FI
RMWARE Appendix 10.3 variod entries A
B AMSTRAD CPC464/664/
6128 FIRMWARE page 20.9 ERA
Action Erase files. Parameters One s
tring parameter. Notes The string parameter is a filenam
e, possibly containing wild cards. All files which match this filenam
e are erased. A file which matches the filename but is marked R/
O Appendix XI The Alternate Register Set. The Z8
0 mircoprocessor has two sets of registers - the normal set (AF, BC, DE
and HL) and the alternate set (AF', BC', DE' and HL'). Unless the tech
niques outlined in this appendix are implemented the user is prohibite
d from using the alternate register set. This is because the alternate
register set is used by the firmware (the Kernel in particular)
for storing certain system valu Pes and flags. Providing that the
user never enters the firmware then the alternate register set may be
used without restriction. Of course this would mean that the user wo
uld be unable to use any facilities provided by the firmware. Fu
rthermore, the user would also have to disable interrupts as interrupts
cause firmware routines to be executed. In the section below a number
of different methods are described that allow the user to overcome the
se restrictions. The method chosen will depend on what use is to be mad
e of the alternate register set. a. The firmware's use of the alternat
e register set. The Kernel stores a couple of system variables in
the alternate register set. This allows the Kernel to access these va
riables easily and thus speeds up a number of operations (particularly
entry to and exit from firmware routines). Only BC' and the alternate
carry flag (carry') are used to store values, however, routines do m
ake use of the other alternate registers and so firmware routines m
ay corrupt them. B' is used to store the I/O address of the g
ate array (#7F). C' is used to store the value required to set the
current ROM state and screen mode Bits 0..1
Set the screen mode. Bit 2 Disables the lower ROM.
Bit 3 Disables the upper ROM. Bits 4
..7 System value to select gate carry function. By changing the
ROM state bits and performing an OUT (C),C instruction the user can enab
le or disable ROMs. (N.B. The Z80 OUT (C),r and IN (C),r instructions
use B as the top 8 bits of the I/O address. The hardware uses these
top bits for decoding the I/O address, it ignores the bottom 8 bits!)
OUT (C),C may be used to change the ROM state during the interrupt
path when the normal Kernel entries (e.g. KL U ROM ENABLE) may not be
called because they enable interrupts. Carry' is normally false. When
carry' is true this indicates that the firmware is in the interrupt pa
th. The firmware occasionally uses this flag to allow it to take a di
fferent action when it is in the interrupt path to the action it t
akes when it is not in the interrupt path (usually avoiding enabling in
terrupts). AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 11.1 b. Simple use of the alternate registe
r set. The technique described in this section allows use of the al
ternate register set providing that no firmware routines are called and
that interrupts are disabled. After disabling interrupts reg
isters A', DE' and HL' may be used as required. If registers BC' or F
' (in particular carry') are used then their original contents must
be restored before interrupts are re-enabled. The user may alter bi
ts in C' (as described in (a) above) and need not restore the original
value provided that an OUT (C),C is performed to keep the hardware abr
east of the current state. The machine will not function correctly
if the hardware and the value in C' are out of step when interrupts ar
e enabled. This technique requires interrupts to be disabled for the d
uration of the operation being performed. This is acceptable if the ope
ration is short but not if the operation is lengthy. Disabling interrup
ts for a lengthy period will stop many firmware functions such as time
rs (and hence ink flashing, sound generation and keyboard scanning).
If the operation to be performed is lengthy then it might be bett
er to consider the use of one of the other techniques described in sec
tions (c) or (d) instead. Example. The user
might want to provide a routine that performs an LD A,(BC) fr
om RAM (similar to the RAM LAM pseudo-instruction provided by
the firmware). The code for this routine could be written as foll
ows AFROMBC PUSH BC DI
** About to use alternate registers EXX
POP HL Transfer BC to HL' LD P A,C
SET 2,A Set the disable lower ROM bit
SET 3,A Set the disable upper ROM bit OUT (C),
A Tell the hardware LD A,(HL)
Read the value from RAM OUT (C),C Restor
e the old ROM state EXX EI
** End of use of alternate registers RET
N.B. This routine must be RAM resident or disabling the ROMs will
have an unfortunate effect! AMSTRAD CPC464/664/6128 FIRMWA
RE Appendix 11.2 c. Use the alternat
e register set with interrupts enabled. The technique described in thi
s section allows the alternate register set to be used and interrupts
to be enabled. It does not allow firmware routines to be called.
The simplistic use of the alternate register set by disa erruptsbling
intas described above is unsatisfactory if this result erruptss in
intbeing disabled for an extended period of time. By patching
INTERRUPT ENTRY in the low Kernel jumpblock interrupts can be trapped
and appropriate action to restore the firmware registers can be taken.
The actions that must be performed are as follows Before st
arting to use the alternate register set the firmware's BC' is sav
ed and INTERRUPT ENTRY is patched so that the user's interrupt r
outine is used. When the user has finished with the alternate re
gister set the firmware's BC' and carry' are restored and INTER
RUPT ENTRY is patched back to the firmware's interrupt routine.
When an interrupt occurs the user's alternate registers are saved,
the firmware's BC' and carry' are restored and INTERRUPT ENTRY is
patched back to the firmware's interrupt routine. The latter is
done in case a second interrupt occurs whilst processing the
events kicked from the interrupt path of the first interrupt
(remember that the event processing is performed with interrupts
enabled). After interrupt processing has finished the fir
mware's BC' is saved, the user's alternate registers are restored
and INTERRUPT ENTRY is patched back to the user's interrupt routin
e again. Note that when INTERRUPT ENTRY is patched it is vital to ens
ure that the lower ROM is disabled and remains disabled. It is imposs
ible to patch the ROM version of INTERRUPT ENTRY! If an interrupt o
ccurred whilst the lower ROM was enabled then the firmware would jump st
raight into its interrupt routine without restoring its alternate regi
sters first. Example. The following routines
implement the scheme described above The following sto
rage locations are used FIRMBC DEFS 2 Two byte
s to store the firmware's BC' FIRMINT DEFS 2 Two bytes to st
ore the address of the firmware's interrupt
routine USERAF DEFS 2 Two bytes to store the user's AF'
USERBC DEFS 2 Two bytes to store the user's BC' U
SERDE DEFS 2 Two bytes to store the user's DE' USERHL
DEFS 2 Two bytes to store the user's HL' AMSTRAD CPC464/66
4/6128 FIRMWARE Appendix 11.3
This routine sets up the environment so that user
may make use of the alternate register set. N.B. Interrupts are
enabled. USERALTERNATE DI
An interrupt would be disastrous EX AF,AF'
EXX Swap to the alternate register set
LD (FIRMBC),BC Save the firmware's BC'
LD HL,(INTERRUPTENTRY+1) LD (FIRMINT),HL
Save the firmware's interrupt
routine LD HL,USERINTERRUPT Use the replacement interrup
t LD (INTERRUPTENTRY+1),HL routine P
LD HL,(USERAF) PUSH HL POP AF
Restore user's AF' LD BC,(USERBC) Restore use
r's BC' LD DE,(USERDE) Restore user's DE'
LD HL,(USERHL) Restore user's HL'
EXX Swap back to the standard register EX
AF,AF' set EI We have f
inished with the RET alternate regs
This routine restores the environment for the
firmware to use the alternate register set. N.B. Interrupt
s are disabled and not re-enabled. FIRMALTERNATE
DI An interrupt would be disasterous
EX AF,AF' EXX Swap the alternat
e register set LD (USERHL),HL Swap user'
s HL' LD (USERDE),DE Swap user's DE'
LD (USERBC),BC Swap user's BC' POP AF
POP HL LD (USERAF),HL Save user's AF'
AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 11.4 LD HL,(FIRMINT) Restor
e the firmware's interrupt LD (INTERRUPTENTRY+1),HL routine
LD BC,(FIRMBC) Restore the firmware's BC'
OR A,A Set the firmware's carry' to be
false EXX Swap
back to the standard register EX AF,AF' set
RET N.B. May be about to enter the
interrupt path so no EI.
This routine replaces the firmware's interrupt routine
when the user is using the alternate register set
USERINTERRUPT CALL FIRMALTERNATE Switch th
e environment to the firmware CALL INTERRUPTENTRY Run the norma
l interrupt routine JP USERALTERNATE Switch the environment
back to the user To start using the alternate register set the
user obeys the instruction CALL USERALTERNATE
To finish using the alternate register set the user obeys the
instructions CALL FIRMALTERNATE EI
d. Calling firmware routines whilst using the alternate register set.
The technique described in this section extends the technique
described in section (c) to allow the user to call firmware routines
whilst using the alternate register set. To call a firmware rout
ine requires exactly the same action as is required for the interru
pt routine Before calling a firmware routine the user's alternate
registers are saved, the firmware's BC' and carry' are res
tored and INTERRUPT ENTRY is patched back to the firmware's
interrupt routine. After running the firmware routine
the firmware's BC' is saved, the user's alternate registers are r
estored and INTERRUPT ENTRY is patched back to the user's interrupt
routine again. As indicated in section 8c) it is vital to ensure that
the lower ROM remains disabled while the alternate register set is
in use since INTERRUPT ENTRY in the ROM is not patchable and jumps str
aight to the firmware's interrupt routine AMSTRAD CPC46
4/664/6128 FIRMWARE Appendix 11.5 Us
ing the routines defined in section (c) a firmware routine may be cal
led by using the following sequence .. C
ALL FIRMALTERNATE Switch the environment to the firmware EI
FIRM ALTERNATE disables interrupts CALL firmware
Run the firmware routine CALL USERALTERNATE Switch the en
vironment back to the user The above code is rather long if a lot of
firmware calls are to be made (10 by Ptes per call). The following
routine takes the address of a firmware routine to call to as an inline
parameter (and only uses 5 bytes per call).
This routine saves the user's alternate registers, calls a
firmware routine whose address is passed inline and then res
tores the user's alternate register set afterwards. F
IRM ROUTINE CALL FIRMALTERNATE Switch to the firmware environme
nt EXX N.B. Interrupts are disable
d POP HL Recover address of routine to call, uses
LD E,(HL) firmware's DE' and HL' which may be
INC HL corrupted LD D,(HL) Get
routine to call into DE' INC HL PUSH HL
Put the real return address back LD HL,USER
ALTERNATERestore the user environment when
the firmware returns by putting a PUSH HL fake retu
rn address on the stack PUSH DE Save t
he routine to call EXX EI RET
Jump to the routine to call To call a firmware rout
ine using the above routine the following sequence should be used
.. CALL FIRMROUTINE fir
mware Address of routine to call ..
FIRM ROUTINE returns here AMSTRAD CPC464/664/6128 FIRMWAR
E Appendix 11.6 wing sequence EXX
EI RET Jump to the routine to call
To call a firmware routine using the above routine the following
sequence should be used .. C12-13BOTBIN
c c N+&''Z*K8!N#F#2 !KG (# #F#AcJx0xyx00001000x008 " p#pp+fxxpxx #0000 000'pxxx
xyx0qpxxxx9qpxxxx9qpxxxxxxxyyyxx 0yyyxx c6nnncnn0yyyxx0 c6nnncnn0yyyxxx c6nnncnn
0yyyxx0yyyxxx0xx00000800 0 k333333k3300 k333333k330 k333333k3300xxZ900p0xx90p0xx
90p0xxZxx x k30330333k3300xk30330333k3300xx k30330333k3300x0x0lllZx0l00lll00lll0
0llZxl 0l 333303330300f00l0333303330300f00l333303330300f00l0lxxx8yyx8yxx8Z9yxx88
x9yxx88xx9yxx88xx xZAxxy8x 0xxy8x 6s3x363xxxy P8x0 6s3x363xxxy8x6s3x363x0xxy8x
xxy8xN+&''''fOxxx8yyx8yxx8Z9yxx88x9yxx88xx9yxx88xx xZAxxy8x 0xxy8x 6s3x363xxxy1
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Afmfffgf fmfffgffmfffgffmfffgffmfffgfpfmfffgffmfffgffmfffgffmfffgflgafcggn gfmff
gmf gfml gfm afffff gfm ac gfmmgcfffg gfmmgclffg gfmmgcfffgjffgIfmgg fmggfmggfmg
g fmggfmggfmggfmggfmggfmggBfmggfmggnafccf flcffl lffoaf fcm&af lffo0f lffocffaff
ffcaf lffocffffca lffoolfcffc lffoolfcffc lffoolfcffcjfflIfoff0fofffofffofffofff
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Appendix XII The Hardware and Hardware Variants A. Pro
cessor. The processor is a Z80A running at a clock frequency of 4
.00 MHz (+or-0.1%). There is logic that stretches MREQ and IORQ using t
he CPU WAIT facility so that the processor can only make one access to
memory each microsecond. The processor NMI pin is pulled up
and made available on the expansion bus. However, a non-maskable interr
upt may cause the firmware to violate various timing constraints an
d so its use is not recommended. The processor interrupt pin is driven
by a flip-flop in the video gate array. This flip-flop is set during ev
ery vertical flyback and every 52 scan lines thereafter until the
next vertical flyback. The interrupt is arranged to occur ap
proximately 2 scans (125 microseconds) into the 8 scan (500 mi
crosecond) vertical flyback signal. The interrupt latch is cleared by
the processor acknowledging the interrupt, or explicitly, using a softw
are command. The top bit of the divide by 52 scan counter is also cle
ared when the processor acknowledges an interrupt occurring after thi
s counter has overflowed. This allows the interrupt system to be expande
d. B. Memory. ROM A single 32K byte ROM is prese
nt on the processor board, but is mapped onto two blocks of 16K in the p
rocessor address space. The lower half of the ROM occupies addresses #
0000 to #3FFF and the upper half occupies addresses #C000 to #FFFF
. These two halves of the ROM can be separately enabled and disabled by
two control latches in the video gate array. On power-up or other sy
stem reset both halves of the ROM are enabled. An expansio
n port signal can be used to disable this internal ROM and allow extern
al ROM(s) to be accessed instead. These are selected by output instru
ctions and replace the upper half of the on-board 32K byte ROM when
selected. RAM On the CPC464 and CPC664 64K bytes of dynamic
RAM are fitted to the processor board at addresses #0000 to #FFFF. On
the CPC6128 128K bytes are fitted and this can be bank switched to be a
ccessed at addresses #0000 to #FFFF (see section 2.5). The lowest 16K
and the top 16K are overlayed when ROM is enabled. Whether the ROM
is enabled or not affects where data is read from, it has no effect o
n write operations which will be correctly performed 'through' the ena
bled ROM to the underlying RAM. AMSTRAD CPC464/664/6128
FIRMWARE Appendix 12.1 VDU SCREEN M
EMORY The display uses 16K of the processor RAM memory as screen
refresh memory. On the 464 and 664 the 16K used can be switch betwe
en the blocks starting at #0000, #4000, #8000 and at #C000 by the to
p two bits (bits 12 and 13) programmed into the HD6845S start ad
dress register. On the 6128 the top two bits select RAM banks 0, 1, 2 o
r 3 to be used (see section 6.4 for further details). The a
rrangement of data in the VDU screen memory is dependent on the VDU mo
de currently selected. In all modes the memory can be considered as cons
isting of 8K 16 bit words. Each word contains either 4, 8, Por 16 pi
xels (P0..Pn) of 1, 2 or 4 bits (B0..Bm) depending on the mode as follow
s A0 Bit Mode 0 Mode 1 Mode
2 0 D7 P0B0 P0B0
P0 B0 0 D6 P1B0 P1B0
P1 B0 0 D5 P0B2 P2B0
P2 B0 0 D4 P1B2 P3B0 P3
B0 0 D3 P0B1 P0B1 P4 B0
0 D2 P1B1 P1B1 P5 B0
0 D1 P0B3 P2B1 P6 B0
0 D0 P1B3 P3B1 P7 B0
1 D7 P2B0 P0B0 P8 B0 1
D6 P3B0 P1B0 P8 B0 1
D5 P2B2 P2B0 P10B0 1
D4 P3B2 P3B0 P11B0 1 D
3 P2B1 P0B1 P12B0 1 D2
P3B1 P1B1 P13B0 1 D1
P2B3 P2B1 P14B0 1 D0
P3B3 P3B1 P15B0 Data for lines 0,8
,16,24.. on the display are packed into the first 2K byte block of the
memory, lines 1,9,17,25.. are packed into the corresponding places
of the next 2K byte block of memory, with lines 7,15,23,31.. occupyin
g the top 2K byte block of the 16K memory area. The bottom 10 bits o
f the HD6845SP start address register define where within these 2K block
s the screen starts. The offset from the start of the 2K byte block is a
lways even and is calculated as twice the register contents modul
o 2K bytes. When data has to be displayed from beyond the end of a 2K b
yte block wrap around occurs to the beginning of the same 2K byte block
. See section 6.4 for a fuller description. AMSTRAD CPC464
/664/6128 FIRMWARE Appendix 12.2 C.
AY-3-8912 Programmable Sound Generator. The PSG is accessed using po
rts A and C of the uPD8255 device. Note that when writing or loading
address to the AY-3-9812 the maximum duration of the write or load
address command with BDIR high is 10 microseconds. The clock input t
o the sound generator is exactly 1.00 MHz. The BC2 signal is tied perm
anently high. On power-up the I/O port should be programmed to input mod
e. The user is advised to use the firmware routine MC SOUND REGISTE
R to write to the PSG. D. HD6845S CRT Controller (HD6845S C
RTC). The character clock to the CRTC occurs for every two bytes
fetched from memory, i.e. every 1.0 microseconds. The first byte of a p
air has an even address, the second has an odd address. In normal ope
ration the internal registers are set up as follows Regi
ster Function PAL SECAM NTSC
0 Horizontal Total 63 63 63 1
Horizontal Displayed 40 40 40 2 H
orizontal Sync. Posn. 46 46 46 3 Vsync., H
sync. widths #8E #8E #8E 4 Vertical Total
38 38 31 5 Vertical Total Adjust
0 0 6 6 Vertical Displayed 25
25 25 7 Vertical Sync. Posn. 30 30
27 8 Interlace and Skew 0 0 0
9 Max. Raster Address 7 7 7 1
0 Cursor Start Raster X X X 11
Cursor End Raster X X X 12 Start
Address (H) X X X 13 Start Address
(L) X X X 14 Cursor (H)
X X X 15 Curso Pr (L) X
X X In the above table the numbers for PAL and SEC
AM standards are indentical. For information on the NTSC R
egister 5 see Appendix XIII. Note that X indicates that software may
vary these numbers during device operation. The firmware only makes
use of the start address register which is used to set the screen ba
se and offset. AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 12.3 E. Video Gate Array. The s
oftware must access this device in order to control the enabling and di
sabling of ROMs, the mode of operation of the VDU and also to load co
lour information for 'inks' into the palette memory. One I/O channel
is used for all commands, the top two bits of data specifying the comma
nd type as follows Bit 7 Bit 6 Use
0 0 Load palette pointer register. 0 1
Load palette memory. 1 0 Load mode and ROM enable
register. 1 1 Bank Switching Register on CPC6128.
MODE AND ROM ENABLE REGISTER This write-only register control
s the VDU mode and ROM enabling as follows Bit 7
1 Bit 6 0 Bit 5 ** Reserved ** (Send
0) Bit 4 Clear raster 52 divider. Bit 3
Upper half ROM disable. Bit 2 Lower half ROM disable.
Bit 1 VDU Mode control MC1. Bit 0 VDU Mode c
ontrol MC0. Writing a 1 to bit 4 clears the top bit of the divide b
y 52 counter used for generating periodic interrupts. Mode
s are defined by the mode control pins as follows MC1
MC0 Mode 0 0 Mode 0, 160 x 20
0 pixels in 16 colours. 0 1 Mode 1, 320 x 200 p
ixels in 4 colours. 1 0 Mode 2, 640 x 200 pixel
s in 2 colours. 1 1 ** Do not use **
The gate array hardware synchronises mode changing to the next
horizontal flyback in order to aid software that requires different
parts of the screen to be handled in different modes. On power-up an
d other system resets, the mode and ROM enable register is set to zero,
enabling both halves of the ROM. AMSTRAD CPC464/664/6128 FIRMWA
RE Appendix 12.4 PALETTE POINTER REG
ISTER This write-only register controls the loading of the VDU
colour palette as follows Bit 7 0
Bit 6 0 Bit 5 ** Reserved ** (send 0)
Bit 4 Palette pointer PR4. Bit 3 Palette pointer PR3.
Bit 2 Palette pointer PR2. Bit 1 Palette
pointer PR1. Bit 0 Palette pointer PR0. Bits PR
0 to PR3 select which ink is to have its colour loaded, providin
g bit PR4 is low. If bit PR4 is high then bits PR0 to PR3 are ignored a
nd the border ink colour is loaded. PALETTE MEMORY This
write-only memory controls the VDU colour palette as follows
Bit 7 0 Bit 6 1 Bit 5 ** Reserved *
* (send 0) Bit 4 Colour data bit CD4. Bit 3
Colour data bit CD3. Bit 2 Colour data bit CD2.
Bit 1 Colour data bit CD1. Bit 0 Colour data bit
CD0. The ink entry pointed at by the palette register is loaded w
ith the colour sent on this channel. The number of colours that need
to be loaded ranges from 2 colours in mode 2 to 16 colours in mode
0. In addition to loading the colours an extra colour data byte must be
sent to this channel to define the border colour. On power-up and o
ther system resets the contents of the palette are undefined, but
the border colour is set to BLACK, to avoid unsightly effects on power-u
p. PThe 32 colour codes are decoded to drive the RGB signals, prod
ucing 27 different colours. The hardware colours are listed in Appendix
V. AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 12.5 BANK SWITCHING REGISTER (CPC6128 only)
This write-only register controls the layout of the bank switcha
ble RAM as follows Bit 7 1 Bit
6 1 Bit 5 ** Reserved ** (send 0) Bit 4
0 Bit 3 0 Bit 2 x Bi
t 1 x Bit 0 x The xxx appearing on bits 0, 1,
and 2 is the code for the selected bank layout, detailed as follows
Code 0 1 2 3 4 5 6 7
Address #C000 3 7 7 7 3 3 3
3 #8000 2 2 6 2 2 2 2 2 #
4000 1 1 5 3 4 5 6 7 #0000
0 0 4 0 0 0 0 0 Selecting Code 0 (The
number sent to the Bank Switch Register would be #C0) will switch the n
ormal default bank layout, i.e. Banks 0..3. The other 64k can be acc
essed by selecting codes 4..7. These switch one of the other 16k bloc
ks into area #4000. See section 2.5 for more details.
AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 12.6 F. uPD8255 Parallel Peripheral Interface
. The PPI as well as the 8 port pins on the PSG are used to interface
to the keyboard and to control and sence miscellaneous signals on th
e processor board. Port A must be programmed either to input or to
output in mode 0 since this port is used for reading and writing to
the PSG. Port B must be programmed to input in mode 0, Port C must be
programmed to output in mode 0 on both halves. Circuitry is p
rovided around the PPI to reset it during system reset. For details of
the operation of the uPD8255 see the NEC product specification.
CHANNEL A (Input or Output) Bit 7 Da
ta/Address DA 7 connected to AY-3-8912. Bit 6 Data/Address D
A 6 connected to AY-3-8912. Bit 5 Data/Address DA 5 connecte
d to AY-3-8912. Bit 4 Data/Address DA 4 connected to AY-3-89
12. Bit 3 Data/Address DA 3 connected to AY-3-8912.
Bit 2 Data/Address DA 2 connected to AY-3-8912. Bit
1 Data/Address DA 1 connected to AY-3-8912. Bit 0 Data/A
ddress DA 0 connected to AY-3-8912. CHANNEL B (Input only)
Bit 7 Datacorder cassette read data. Bi
t 6 Centronics busy signal. Bit 5 Not expansion port acti
ve signal. Bit 4 Not option link LK4. Bit 3
Not option link LK3. Bit 2 Not option link LK2.
Bit 1 Not option link LK1. Bit 0 Frame flyback p
ulse. The option links, LK1..LK4 are factory set. LK4 is fitted for
60 Hz T. V. standards and omitted for 50 Hz standards.
CHANNEL C (Output only) Bit 7 AY-3-8912 BDIR signal.
Bit 6 AY-3-8912 BC1 signal. Bit 5 Datacor
der cassette write data. Bit 4 Datacorder cassette motor on.
Bit 3 Keyboard row select KR3. Bit 2 Ke
yboard row select KR2. Bit 1 Keyboard row select KR1.
Bit 0 Keyboard row select KR0. AMSTRAD CPC464/664/
6128 FIRMWARE Appendix 12.7 ADDRESflags
are passed to the target routine untouched except for IY (which is
set to point at a background ROM's upper data area). Exit con
ditions IY preserved. All registers and flags are as set by th
e target routine. Notes The restart instruction takes a 2 by
te inline parameter which is the address of a 'far address'. The 'far
address' is laid out as follows Byte 0 1 2
P G. Centronics Port Latch.
This latch is loaded with data by output commands to the correct I/O
channel. It cannot read. Note that the timing requirements on C
entronics interfaces generally specify that the data must be present on
the seven data lines at least 1 microsecond before the strobe is mad
e active and must remain valid for at least 1 microsecond after the stro
be returns inactive. The duration of the strobe must be between 1 and 5
00 microseconds. The busy signal can be inspected as soon as the strobe
is inactive in order to determine when more data can be sent.
Bit 7 Centronics strobe signal (1 active). Bit 6 Data
7 to Centronics port. Bit 5 Data 6 to Centronics port.
Bit 4 Data 5 to Centronics port. Bit 3 Data 4
to Centronics port. Bit 2 Data 3 to Centronics port.
Bit 1 Data 2 to Centronics port. Bit 0 Data 1
to Centronics port. On power-up and other system resets the outputs
of this latch are all cleared. H. Keyboard and Joysticks.
The keyboard and joystick switches are sensed by selecting one of te
n rows using the four control bits on channel C of the PPI and reading
the data from the PSG parallel port using port A of the PPI.
The keyboard and joystick switches are arranged in a 10 by 8 matrix.
One of ten rows is selected using the code on KR0..KR3 and the eight
bits of data are then read in parallel on a parallel port as described a
bove. A switch is active (closed) if the corresponding data bit is a lo
gic 0. The key number associated with each key (see Appendix
I) is constructed as follows Bit 7
6 5 4 3 2 1 0
0
Row number Bit number Thus the
key that is associated with bit 5 in row 4 has key number 37 (4 * 8 +
5). AMSTRAD CPC464/664/6128 FIRMWARE A
ppendix 12.8 I. Disc Interface. Floppy Disc Contro
ller The controller uses an NEC type uPD765A Floppy Disc Controller I
C to connect to the disc drives. Only two disc drives are supported, s
ince the US1 line from the uPD765A is ignored. This results in two d
isc drives being accessed as drives 0 (zero) and 1 (one) and again
as drives 2 and 3. The controller supports both single and double side
d and single and double density mini-floppy disc drives. Note that the
clock frequency supplied to the uPD765A CLK pin is 4.00 MHz rather
than the 8.00 MHz used with larger disc drives. The full fac
ilities described in the NEC data sheet for the uPD765A are available
with the exception of interrupts and DMA which are not supported.
Expansion ROM. The disc ROM is normally number #07, bit may
be set to #00 by cutting option trace LK1 in the case of the DDI-1, LK
7 in the case of the 664, LK201 in the case of the 6128. The
EXP signal (pin 48), of the 50 way expansion connector, is grou
nded when the disc ROM number is #07 in order that this address can b
e avoided by other expansion peripherals. A 200 nanosecond 27128 type E
PROM or ROM is normally used, and may be fitted in a DIL socket in some
machines. Option trace LK2 and LK3 are manufacturing options
for write pre-compensation. They should not be needed by the user.
Motor Control. Writing to channel #FA7E starts and stop
s the disc drive motors. Writing #00 will stop the motors, #01 wi
ll start the motors. On power-up and other system resets the motors
are not stopped. Electrical Levels All electrical levels
on the controller are TTL compatible. Signals originating in the dri
ves are terminated by 680 ohm resistors to +5v at the controller and r
eceived with gates with input hysteresis. PThe maximum permissable c
able length is .075 metre. AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 12.9 Using Other Disc Drive
s It is possible to use other disc drives with the CPC range
of computers (or the DDI-1), in particular 5.25 inch drives. Som
e hardware knowledge will be required. The following gives some advice
and information which should assist in using a different drive.
If Drive A the 5V power should be supplied to pins 2, 4, 6 and 14
of the 5.25 drive after ensuring that any existing connections to
the drive circuitry have been removed. If Drive B no terminati
ng resistor should be installed. The drive MUST have a 'READY' sig
nal on pin 34. The drive will require its own power supply.
The extra cable should be as short as possible and should consist
of a cable-mounted male connector (to mate with the female socket
connector on the cable from the interface), all 34 conductors and,
normally, a 34 way double-sided card edge connector (to mate with
the 5.25 inch drive). The step rate, motor on and off timeout
may have to be changed, see, in the case of CP/M 2.2, the SETUP u
tility. A drive such as the Shugart 201 is not suitable since it does
not have a ready signal, but one such as the Chinon F 051-MD is suitable
. Pin Arrangement All odd numbered pins are pulled to groun
d (GND). All signals are active low. PIN No.
SIGNAL 2 + 5V 4
+ 5V 6 + 5V
8 INDEX 10 Drive select 0
12 Drive select 1 14
+ 5V 16 Motor On 18
Direction Select 20 Step
22 Write Data 24 W
rite Gate 26 Track 0 28
Write Protect 30 Read Data
32 Side 1 Select 34
Ready AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 12.10 J. Serial Interface The BIOS s
upports a two channel asynchronous serial interface. The interface i
s an optional extra for the CPC 464/664/6128 computers. This section
describes the recommended hardware configuration for the serial interf
ace such that, if fitted, it can be driven by the BIOS. The interfac
e consists of a Zilog Z80A SIO/0 or Z80A DART together with an Intel
8253 programmable interval timer. The 8253 is used as a Baud rate gene
rator as follows Timer 0 generates the transmit clock for channe
l A of the SIO. Timer 1 generates the receive clock for channel
B of the SIO. Timer 0 generates both transmit and receive clocks
for channel B of the SIO. It is assumed that the CLK
inputs to all three channels of this device are driven by a 2.0(0.1%)MHz
clock signal derived from the 4.0 MHz CPU clock. The GATE inputs to all
three channels are tied permanently high. NOTE This is
an optional extra for all machines.
AMSTRAD CPC464/664/6128 FIRMWARE App
endix 12.11 K. I/O ports The following is a deta
iled list of the Z80 I/O used by the CPC range of computers.
PORT OUTPUT INPUT #7Fxx
Video Gate Array ** Do not use ** #BCxx
HD6845 CRTC address ** Do not use ** #BDxx HD6845 CR
TC data ** Do not use ** #BExx ** Do not use **
Reserved for CRTC status #BFxx ** Do not use **
HD6845 CRTC data #DFxx Expansion ROM select
** Not used ** #EFxx Centronics latch ** Do
not use ** P #F4xx uPD8255 port A data
uPD8255 port A data #F5xx uPD8255 port B data uPD8
255 port B data #F6xx uPD8255 port C data uPD8255 po
rt C data #F7xx uPD8255 control ** Undefined **
#F8xx Expansion bus Expansion bus #F9x
x Expansion bus Expansion bus #FAxx
Expansion bus Expansion bus #FBxx Expansion
bus Expansion Bus #FF ** Not used **
** Not used ** Disc Interface #FA7E
Motor Control * not used * #FB7E ** not used
** uPD765A Status Register #FB7F uPD765A Data
Register uPD765A Data Register Serial Interface #FADC
SIO Channel A Data SIO Channel A Data #FADD
SIO Channel A Control SIO Channel A Control #FADE
SIO Channel B Data SIO Channel B Data #FADF SIO C
hannel B Control SIO Channel B Control #FBDC 8253 Load
Counter 0 8253 Read Counter 0 #FBDD 8253 Load Count
er 1 8253 Read Counter 1 #FBDE 8253 Load Counter 2
8253 Read Counter 2 #FBDF 8253 Write Mode Word
** not used ** AMSTRAD CPC464/664/6128 FIRMWARE
Appendix 12.12 Expansion bus I/O channels in the ad
dress range #F800 to #FBFF are reserved as follows AD
DRESS (A0..A7) USE #00..#7B ** Do not use **
#7C..#7F Reserved for Disc Interface. #80..
#BB ** Do not use ** #BC..#BF Reserved fo
r future use. #C0..#DB ** Do not use ** #
DC..#DF Reserved for communications interfaces. #E0..#
FE Available for user peripherals. #FF
Reset peripherals. L. Hardware Variants There have be
en slight differences with the circuitry concerning the ULA in some of
the CPC range of computers, but as long as legal values are used when
accessing them, there should be no noticeable difference.
The firmware has been altered for a few foreign computers. The major
changes have been to the character set (to provide a few new national
characters) and to the characters available on the keyboard (to allow
new characters to be entered), also some messages and version numbers
have been changed. These foreign changes are detailed below. rocessor is a
Z80A rs are used when accessing them, there should be no noti
ceable difference. The firmware ha Start Up Me
ssage The V1 or V3 message at start-up has been changed to S1 or
S3. Identification The ROM modification byte (at loca
tion #C003 in the on-board ROM) is now 1, not 0. Pri
nter Certain Codes have been changed for the printer translation
s. CPC6128 printer codes are unchanged. CPC464 t
ranslations changed are #A1 - #5C
#AB - #7C #AE - #5D
#AF - #5B ioication The ROM
modification byte (at location #C003 in the on-board ROM) is n
ow 1, not 0. Printer Certain Codes have been changed f
or the printer translations. CPC6128 printer codes are unchanged
. CPC464 translations changed are #A1 - #5C
#AB Control versions have moved with ke
ys/chars (as expected). Start Up Messages The V1 or V3
message at start-up has been changed to d1 or d3. Identification
The ROM modification byte (at location #C003 in the on-board
ROM) is now 2 and not 0. AMSTRAD CPC464/664/6128 FIRMWA
RE Appendix 12.14 e moved with keys/chars (as expected).
Start Up Messages The V1 or V3 mes !P!!!!!!!!!id dis
sid dis sid dis sid dis sid dis sidd# ,"Please insert Disc " dis" side " sid"
and press any key..." O "!"fil £#, H H* 4O4 "!"fil £#, R
#, R-H#,!,#,"Press a key.." # Start Up Message Th
e V1 or V3 message at start-up has been changed to f1 or f3. Identific
ation The ROM modification byte (at location #C003 in the on
-board ROM) is now 3, not 0. AMSTRAD CPC464/664/61
28 FIRMWARE Appendix 12.15 anged to f1 or f3.
Identificatio. An example of how to use these commands can be found in s
ection 10.7. N.B The BIOS extended jumpblock itself is not availab
le, indeed it does not exist in an AMSDOS environment. The
BIOS routines available and their command names are as follows
SET MESSAGE Ctrl A (#01) SET UP DISC
Ctrl B (#02) SELECT FORMAT
Ctrl C (#03) READ SECTO Keyboard
So many characters have been moved around that it is easiest to
show the changes with the following diagram. The control versions
have moved with the keys/chars (as expected). the changes be patched a
s required. For more details on this see section 9.9.
AMSTRAD CPC464/664/6128 FIRMWARE
page 19.1 When one of these routines fails (carry f
alse) it returns an error number in the A register. This is referred
to in the following pages as the 'error status byte'. If bit 7 of thi
s byte is set then the error as already been reported to the u
ser. Bit APEN12 BASp(rt.bas"$$, "Please insert disc 1 side 1 and pres P , ,
fil"apen-12.p1" fil"apen-12.p2" , "Please wait for printer to stop then press
a key to continue..." 9( li #"12-13bot", DUM,2 li ##,()"AMSTRAD CPC464/664/
6128 FIRMWARE Appendix 12.13" li #fil"apen-12.p4" OF l
i #"12-14bot", DUM, li #Pfil"apen-12.p5" 6Z li #"f-sys", DUM,Jd li #fil"a
pen-12a.p6" li #7n"FRENCH", DUM, li #xfil"apen-12.p6" #"!"fil £#,#, #,
,P,, £8M , "Please insert disc 1 side 1 and press any key.." "start.bas"$$, "Pl
ease insert disc 1 side 1 and press any key.." "start.bas"3. Identific
atioli #"f-sys", DUM,Jd li #fil"apen-12a.p6" li #7n"FRENCH", DUM, li #x
fil"apen-12.p6" #"!"fil £#,#, #,,P,, £8M , "Please insert disc 1 side 1 and
press any key.." "sta#fil"apen-12.p4" AF li #"12-14bot", DUM, Pfil"apen-12.p
5" 'Z "f-sys", DUM,,d fil"apen-12a.p6" (n"FRENCH", DUM, %xfil"apen-12.p6" #
"!"fil £#,#, #,,P,, £8M , "Please insert disc 1 side 1 and press any key.." "
start.bas" f3. Identificatio "P"""""""""F-SYS BINppppp ppZ*K8!N#F#2
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